LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY bench_ IS
END tbProcesseurAndCo;

ARCHITECTURE behavior OF tbProcesseurAndCo IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ProcesseurEtCo
	PORT(
		CLK : IN std_logic;
		RST : IN std_logic;
		HS,VS,R,G,B : OUT STD_LOGIC;
		PIN : IN std_logic_vector(15 downto 0);          
		POUT : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL CLK :  std_logic := '0';
	SIGNAL RST :  std_logic := '0';
	SIGNAL PIN :  std_logic_vector(15 downto 0) := (others=>'0');

	--Outputs
	SIGNAL POUT :  std_logic_vector(15 downto 0);
--	SIGNAL HS,VS,R,G,B : std_logic;
BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ProcesseurEtCo PORT MAP(
		CLK => CLK,
		RST => RST,
		PIN => PIN,
		POUT => POUT
--		HS=>HS,VS=>VS,R=>R,G=>G,B=>B
	);
	process 
	begin
		CLK<='1';
		wait for 10 ns;
		CLK<='0';
		wait for 10 ns;
	end process;
	tb : PROCESS
	BEGIN
		RST<='1';
		PIN<=x"0003";
		-- Wait 100 ns for global reset to finish
		wait for 101 ns;
		RST<='0';
		wait for 401 ns;
		PIN<=x"0FF0";
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;
